Key ASIC secures IP deal for wafer fab worth RM21 million

Key ASIC has secured a contract with Canvas Technology, for the first part of the project valued at RM21 million to provide product, technology and design IP development strategy, planning and implementation for a wafer fab.  

There was a surge in the construction of new fabs or repurpose of existing wafer fabs. As reported by SEMI in August 2019, 33 new wafer fabs were under construction and over 50 of the existing fabs are repurposed for the current technologies to meet the market trend.

Chairman and Chief Executive Officer (CEO) of Key ASIC, Eg Kah Yee emphasised that the recent surge on the construction of new fabs taking place two years, added up to the market capitalization, of semiconductors exceeded US$4 trillion. This is largely driven by the digitalisation of the economy globally.

“The steep growth of new wafer fabs in the past two years has created strong demand for technologies and silicon proven SoC platform-based IP. With the rapid development of IOT and AI coupled with the severe shortage of chips and capacity across the board, the demand for technologies and Design IPs will continue to grow in the foreseeable future,” Eg said.

Notably, leading this wave of development is China with spending of USD24B followed by Taiwan with spending of $13B and Europe and Mideast with spending of US$11 billion. This created a strong demand for licensing of technologies and Design IPs so that these expensive fabs can churn out chips at the earliest, reducing the time to revenue.

KeyWareTM, the Standard Cell libraries that are ultra-low power or high performance, is uniquely giving the wafer fabs a strong competitive advantage. Chips that are designed using the libraries of ultra-low power will be able to reduce power consumption by about 30 percent on the same process.

Technology and chips that are designed using the Standard Cell libraries of high performance will be able to increase the speed of the chip by about 30 percent on the same process technology enabling the chip designers to develop highly competitive products in the market.

In addition to KeyWareTM, the Company has a rich pool of silicon proven and standard compliant IPs such as USB2.0, USB3.0, PCi-e 1.2, PCi-e 2.0 and Ethernet, memory blocks, I/Os, a full spectrum of ADC, DAC and AFEs, total of more than 100 IP blocks that are commonly used in the design of SoCs. These IPs are essential for the design of SoCs in IOT, AI, smart home, industry 4.0, consumer and communication.

The project is planned to have multiple parts and contracts of subsequent parts expected to follow in the near future.

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